Notes by Alisha Ukani
Virtual Memory
- VM allows us to isolate address spaces — we can protect the kernel from interference by processes + protect processes from each other
- Only kernel (privileged code) gets access to dangerous features from hardware, like shut down computer
- A page table is a data structure (basically radix tree) that maps memory
- Maintained by privileged code
- Interpreted by hardware
- The IOMMU (I/O Memory Management Unit) part of the computer knows how to reach a given address
- First, it'll check the translation lookaside buffer (a cache the processor can't access) for the mapping
- Then, it'll check the page table
- Linear address = virtual address
- 36 bits (because the page offset is 12 bits, so together that's 48 bits, or the bits that we're allowed to use in a 64-bit address)
- For a 64 bit virtual address:
- Only some addresses are canonical, and only canonical addresses can be dereferenced
- In canonical addresses, the top 16 bits are either all 0 or all 1
- If bit 47 is 0, then bits 48-63 must be 0x0000
- If bit 47 is 1, then bits 48-63 must be 0xffff
- So only the following virtual addresses are canonical:
0x0000'0000'0000'0000
to0x0000'7fff'ffff'ffff
inclusive (low canonical)0xffff'8000'0000'0000
to0xffff'ffff'ffff'ffff
inclusive (high canonical)
- Bits 0-11 are the page offset, preserved as virtual address goes through page tables
- Bits 12-47 comprise 4 page table indices, each is 9 bits:
- Bits 12-20 are the L1 index
- Bits 21-29 are the L2 index
- Bits 30-38 are the L3 index
- Bits 39-47 are the L4 index
- Page table can say that an address can't be cached, or you can't execute code at this address
- Page size is 4096 (2^12) bytes
- The
%cr3
register tells us where the top page table is - The translation lookaside buffer has mappings that cover large amounts of memory (like a full GB) so every mapping in that range will hit the destination page table and then skip loading 5 addresses from memory
- So, if we get PTE_PS flag, we stop checking
Chickadee early pagetable
- Lowest 510 GiB (low canonical addresses) and highest 510 GiB (high canonical addresses) map on to physical addresses
- Low canonical is on left, high canonical on right
- Highest 2 GiB (virtual address -1) mapped to lowest 2 GiB of physical memory
- Kernel text addresses: this is where the kernel's code (read-only data) lives
- Code runs in either the very lowest or very highest 2 GiB of memory
- Most addresses fault because we
memset
to 0 - The loop is installing 510, 1GiB mappings
- Kernel uses the high portion of virtual memory
Assembly review
- Quadword = 64 bits = 8 bytes
- Size of register is 64 bits (when we use the r prefix)
- Source on left, destination on right